The present invention relates in general to integrated circuitry, and in particular to a complementary metal-oxide-semiconductor (CMOS) logic family with enhanced speed characteristics.
For a number of reasons CMOS is the logic family of choice in today""s VLSI devices. Due to the complementary nature of its operation, CMOS logic consumes zero static power. CMOS also readily scales with technology. These two features are highly desirable given the drastic growth in demand for low power and portable electronic devices. Further, with the computer aided design (CAD) industry""s focus on developing automated design tools for CMOS based technologies, the cost and the development time of CMOS VLSI devices has reduced significantly.
The one drawback of the CMOS logic family, however, remains its limited speed. That is, conventional CMOS logic has not achieved the highest attainable switching speeds made possible by modern sub-micron CMOS technologies. This is due to a number of reasons. Referring to FIG. 1, there is shown a conventional CMOS inverter 100xe2x80x94the most basic building block of CMOS logic. A p-channel transistor 102 switches between the output and the positive power supply Vcc, and an n-channel transistor 104 switches between the output and the negative power supply (or ground). The switching speed in CMOS logic is inversely proportional to the average on resistance (Ron) of the MOS transistor, and the load capacitance CL on a given node (xcfx84=Ronxc3x97CL). The on resistance Ron is proportional to the transistor channel length L divided by the power supply voltage (i.e., Ron xcex1 L L/Vcc), while the load capacitance is given by the gate capacitance of the transistor being driven (i.e., Wxc3x97Lxc3x97Cox, where Cox is the gate oxide capacitance), plus the interconnect parasitic capacitance Cint. Therefore, with reduced transistor channel lengths L, the switching speed is generally increased. However, this relationship no longer holds in sub-micron technologies. As the channel length L in CMOS technology shrinks into the sub-micron range, the power supply voltage must be reduced to prevent potential damage to the transistors caused by effects such as oxide breakdown and hot-electrons. The reduction of the power supply voltage prevents the proportional lowering of Ron with the channel length L. Moreover, the load capacitance which in the past was dominated by the capacitances associated with the MOS device, is dominated by the routing or interconnect capacitance (Cint) in modern sub 0.5 micron technologies. This means that the load capacitance will not be reduced in proportion with the channel length L. Thus, the RC loading which is the main source of delaying the circuit remains relatively the same as CMOS technology moves in the sub-micron range.
As a result of the speed limitations of conventional CMOS logic, integrated circuit applications in the Giga Hertz frequency range have had to look to alternative technologies such as ultra high speed bipolar circuits and Gallium Arsenide (GaAs). These alternative technologies, however, have drawbacks of their own that have made them more of a specialized field with limited applications as compared to silicon MOSFET that has had widespread use and support by the industry. In particular, compound semiconductors such as GaAs are more susceptible to defects that degrade device performance, and suffer from increased gate leakage current and reduced noise margins. Furthermore, attempts to reliably fabricate a high quality oxide layer using GaAs have not thus far met with success. This has made it difficult to fabricate GaAs FETs, limiting the GaAs technology to junction field-effect transistors (JFETs) or Schottky barrier metal semiconductor field-effect transistors (MESFETs). A major drawback of the bipolar technology, among others, is its higher current dissipation even for circuits that operate at lower frequencies.
It is therefore highly desirable to develop integrated circuit design techniques that are based on conventional silicon CMOS technology, but overcome the speed limitations of CMOS logic.
The present invention provides a new family of CMOS logic that is based on current-controlled mechanism to maximize speed of operation. The current-controlled CMOS (or C3MOS(trademark)) logic family according to the present invention includes all the building blocks of any other logic family. The basic building block of the C3MOS logic family uses a pair of conventional MOSFETs that steer current between a pair of load devices in response to a difference between a pair of input signals. Thus, unlike conventional CMOS logic, C3MOS logic according to this invention dissipates static current, but operates at much higher speeds. In one embodiment, the present invention combines C3MOS logic with CMOS logic within the same integrated circuitry, where C3MOS is utilized in high speed sections and CMOS is used in the lower speed parts of the circuit.
Accordingly, in one embodiment, the present invention provides a current-controlled metal-oxide-semiconductor field-effect transistor (MOSFET) circuit fabricated on a silicon substrate, including a clocked latch made up of first and second n-channel MOSFETs having their source terminals connected together, their gate terminals coupled to receive a pair of differential logic signals, respectively, and their drain terminals connected to a true output and a complementary output, respectively; a first clocked n-channel MOSFET having a drain terminal connected to the source terminals of the first and second n-channel MOSFETs, a gate terminal coupled to receive a first clock signal CK, and a source terminal; third and fourth n-channel MOSFETs having their source terminals connected together, their gate terminals and drain terminals respectively cross-coupled to the true output and the complementary output; a second clocked n-channel MOSFET having a drain terminal connected to the source terminals of the third and fourth n-channel MOSFETs, a gate terminal coupled to receive a second clock signal CKB, and a source terminal; first and second resistive elements respectively coupling the true output and the complementary output to a high logic level; and a current-source n-channel MOSFET connected between the source terminals of the first and second clocked n-channel MOSFETs and a logic low level.
In another embodiment, the circuit further includes a buffer/inverter made up of first and second n-channel MOSFETs having their source terminals connected together, their gate terminals respectively coupled to receive a pair of differential logic signals, and their drain terminals coupled to a high logic level via a respective pair of resistive loads; and a current-source n-channel MOSFET connected between the source terminals of the first and second n-channel MOSFETs and a low logic level, wherein, the drain terminal of the first n-channel MOSFET provides a true output of the buffer/inverter and the drain terminal of the second n-channel MOSFET provides the complementary output of the buffer/inverter.
In yet another embodiment, the present invention provides complementary metal-oxide-semiconductor (CMOS) logic circuitry that combines on the same silicon substrate, current-controlled MOSFET circuitry of the type described above for high speed signal processing, with conventional CMOS logic that does not dissipate static current. Examples of such combined circuitry include serializer/deserializer circuitry used in high speed serial links, high speed phase-locked loop dividers, and the like.
The following detailed description with the accompanying drawings provide a better understanding of the nature and advantages of the current-controlled CMOS logic according to the present invention.